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| gennum corporation p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 e-mail: info@gennum.com www.gennum.com revision date: november 2000 document no. 521 - 63 - 05 preliminary data sheet gs9025 features ? smpte 259m compliant operational to 540mb/s automatic cable equalization (typically greater than 350m of high quality cable at 270mb/s) adjustment-free operation auto-rate selection (5 rates) with manual override single external vco resistor for operation with five input data rates data rate indication output system friendly: serial data outputs muted and serial clock remains active when input data is lost operation independent of sav/eav sync signals signal strength indicator output output 'eye' monitor (oem) with large signal amplitude and power down option carrier detect with programmable threshold level power savings mode (output serial clock disable) 44 pin mqfp applications cable equalization plus clock and data recovery for all high speed serial digital interface applications involving smpte 259m and other data standards. description the gs9025 provides automatic cable equalization and high performance clock and data recovery for serial digital signals. the gs9025 receives either single-ended or differential serial digital data and outputs differential clock and retimed data signals at pecl levels (800mv). the on- board cable equalizer provides up to 40db of gain at 200mhz which typically results in equalization of greater than 350m of high quality cable at 270mb/s. the gs9025 operates in either auto or manual data rate selection mode. in both modes, the gs9025 requires only one external resistor to set the vco centre frequency and provides adjustment free operation. the gs9025 has dedicated pins to indicate signal strength/carrier detect, lock and data rate. optional external resistors allow the carrier detect threshold level to be customized to the user's requirement. in addition, the gs9025 provides an 'output eye monitor' (oem) which allows the verification of signal integrity after equalization, prior to reslicing. the serial clock outputs can be disabled to reduce power consumption. the gs9025 operates from a single +5 or -5 volt supply. block diagram ordering information part number package temperature GS9025-CQM 44 pin mqfp tray 0c to 70c gs9025-ctm 44 pin mqfp tape 0c to 70c lf+ lfs lf- cbg r vco carrier detect phaselock harmonic frequency acquisition vco division 3 bit counter lock sdo sdo clk_en sco sco smpte auto/man ss0 ss1 ss2 mute cosc a/d phase detector decoder logic analog digital mux ddi + - ddi sdi sdi oem agc cap cd_adj auto eq control eye monitor variable gain eq stage charge pump + - + - ssi/cd genlinx ? ii gs9025 serial digital receiver
gennum corporation 521 - 63 - 05 2 gs9025 absolute maximum ratings parameter value supply voltage (v s )5.5v input voltage range (any input) v cc +0.5 to v ee -0.5v operating temperature range 0c t a 70c storage temperature range -65c t s 150c lead temperature (soldering, 10 sec) 260c dc electrical characteristics v cc = 5.0v, v ee = 0v, t a = 0c to 70c unless otherwise shown. parameter symbol conditions min typ max units notes test level supply voltage v cc 4.75 5.0 5.25 v 1 supply current s clk_en = 0 - 115 - ma 1 clk_en = 1 - 125 - ma 1 clk_en = 0, oem active - 135 - ma 1 clk_en = 1, oem active - 145 - ma 1 sdi/sdi common mode voltage -2.5-v 1 ddi/ddi common mode input voltage range v ee +(v diff /2) 0.4 to 4.6 v cc -(v diff /2) v 1 1 ddi/ddi differential drive 200 800 2000 mv 1 agc+/agc- common mode voltage -2.7-v 1 oem bias potential - 4.5 - v ssi/cd output current v ssi/cd = 2.4v - +120 - a 3 v ssi/cd = 0.4v (muted) - -1.0 - ma auto/man , smpte, ss[2:0] input voltage high 2.0 - - v 3 1 low - - 0.8 v clk_en input voltage high 2.5 - - v 1 low - - 0.8 v lock output sink current 500 - - a 4 1 ss[2:0] output voltage high 4.4 4.7 - v 3 1 low - 0.2 0.4 v ss[2:0] source current auto mode 180 300 - a 3 1 gennum corporation 521 - 63 - 05 3 gs9025 fig. 1 test setup for figures 6 - 11 ss[2:0] sink current auto mode 0.6 1 - ma 3 1 ss[2:0] source current manual mode - - 0 a 3 1 ss[2:0] sink current manual mode - 0.8 5 a 3 1 notes 1. v diff is the differential input signal swing. 2. see description. 3. pins ss[2:0] are outputs in auto mode and inputs in manual mode. 4. lock is an open collector output and requires an external pullup resistor. test levels 1. 100% tested at 25c. 2. guaranteed by design. 3. inferred or correlated value. ac electrical characteristics v cc = 5.0v, v ee = 0v, t a = 0c to 70c unless otherwise shown. r lf = 1k ? , c lf1 = 15nf, c lf2 = 5.6pf parameter symbol conditions min typ max units notes test levels data rate 143 - 540 mb/s 1 maximum equalizer gain at 200mhz - 40 - db additive jitter t j 270mb/s, 300m - 300 - ps p-p see figs 7-11 1 540mb/s, 100m - 275 - ps p-p jitter transfer function peaking --0.1db 2 frequency drift when pll loses lock -15 % 2 lock time synchronous switch t switch < 0.5s, 270mb/s -1- s 1 2 0.5s gennum corporation 521 - 63 - 05 4 gs9025 pin connections pin descriptions number symbol type description 1, 2 ddi/ddi i digital data inputs (differential ecl/pecl). 3, 44 v cc _75 i power supply connection for internal 75 ? pullup resistors connected to ddi/ddi . 4, 8, 13, 22, 35 v cc i most positive power supply connection. 5, 9, 14, 18, 27, 30, 33, 34, 37 v ee i most negative power supply connection. 6, 7 sdi/sdi i differential analog data inputs. 10 cd_adj i carrier detect threshold adjust. 11, 12 agc-, agc+ i external agc capacitor. 15 lf+ i loop filter component connection. 16 lfs i loop filter component connection. 17 lf- i loop filter component connection. 19 r vco _rtn i frequency setting resistor return connection. 20 r vco i frequency setting resistor connection. 21 cbg i internal bandgap voltage filter capacitor. 23, 24, 25 ss[2:0] i/o data rate indication (auto mode) or data rate select (manual mode). ttl/cmos compatible i/o. in auto mode these pins can be left unconnected. 26 auto/man i auto or manual mode select. ttl/cmos compatible input. ddi ddi v cc _75 v cc v ee sdi sdi v cc v ee cd_adj agc- sdo sdo v ee sco sco v ee auto/man ss0 ss1 ss2 gs9025 top view agc+ v cc v ee lf+ lfs lf- v ee r vco _rtn r vco cbg v cc v cc _75 oem smpte a/d ssi/cd lock cosc v ee clk_en v cc v ee v ee 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 gennum corporation 521 - 63 - 05 5 gs9025 28, 29 sco /sco o serial clock output. sco /sco are differential current mode outputs and require external 75 ? pullup resistors. 31, 32 sdo /sdo o equalized and reclocked serial digital data outputs. sdo /sdo are differential current mode outputs and require external 75 ? pullup resistors. 36 clk_en i clock enable. when high, the serial clock outputs are enabled. 38 cosc i timing control capacitor for internal system clock. 39 lock o lock indication. when high, the gs9025 is locked. lock is an open collector output and requires an external 10k ? pullup resistor. 40 ssi/cd o signal strength indicator/carrier detect. 41 a/d i analog/digital select. 42 smpte i smpte/other data rate select. ttl/cmos compatible input. 43 oem o output ?eye? monitor. oem is a single ended current mode output and requires an external 50 ? pullup resistor. pin descriptions (continued) number symbol type description gennum corporation 521 - 63 - 05 6 gs9025 typical performance curves (v s = 5v, t a = 25c unless otherwise shown) fig. 2 ssi/cd voltage vs. cable length (belden 8281)(cd_adj = 0v) fig. 4 carrier detect adjust voltage threshold characteristics fig. 6 error free cable length vs. data rate fig. 3 equalizer gain vs. frequency fig. 5 input impedance fig. 7 additive jitter vs. input cable length (belden 8281) 0 50 100 150 200 250 300 350 400 450 500 5.00 4.50 4.00 3.50 3.00 2.50 cable length (m) ssi/cd output voltage (v) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 200 250 300 350 400 cable length (m) cd_adj voltage (v) 150 200 250 300 350 400 450 90 180 270 360 450 540 630 typical error free cable length (m) data rate (mb/s) 0 5 10 15 20 25 30 35 40 45 50 1 10 100 1000 gain (db) frequency (mhz) 270 j1 3000 1620 810 -j1 -j2 -j5 j5 j2 j0.2 -j0.2 -j0.5 j0.5 frequencies in mhz, impedances normalized to 50 ? 0 50 100 150 200 250 300 350 400 450 0 100 200 300 400 additive jitter p-p (ps) cable length (m) 540mb/s 270mb/s gennum corporation 521 - 63 - 05 7 gs9025 fig. 8 output jitter (143mb/s, 300m) fig. 10 output jitter (360mb/s, 300m) fig. 9 output jitter (270mb/s, 300m) fig. 11 output jitter (540mb/s, 100m) detailed description the gs9025 serial digital receiver is a bipolar integrated circuit containing a built-in cable equalizer and reclocker. serial digital signals are applied to either the analog sdi/sdi or digital ddi/ddi inputs. signals applied to the sdi/sdi inputs are equalized and then passed to a multiplexer. signals applied to the ddi/ddi inputs bypass the equalizer and go directly to the multiplexer. the analog/digital select pin (a/d ) determines which signal is then passed to the reclocker. packaged in a 44 pin mqfp, the receiver operates from a single 5v supply to data rates of 540mb/s. typical power consumption is 575mw. 1. cable equalizer the automatic cable equalizer is designed to equalize serial digital data signals between 30mb/s and 540mb/s. the serial data signal is connected to the input pins (sdi/sdi ) either differentially or single ended. the input signal passes through a variable gain equalizing stage whose frequency response closely matches the inverse cable loss characteristic. in addition, the variation of the frequency response with control voltage imitates the variation of the inverse cable loss characteristic with cable length. the gain stage provides up to 40db of gain at 200mhz which typically results in equalization of greater than 350m at 270mb/s of belden 8281 cable. the edge energy of the equalized signal is monitored by a detector circuit which produces an error signal corresponding to the difference between the desired edge energy and the actual edge energy. this error signal is integrated by an external differential agc filter capacitor (agc+/agc-) providing a steady control voltage for the gain stage. as the frequency response of the gain stage is automatically varied by the application of negative feedback, the edge energy of the equalized signal is kept at a constant level which is representative of the original edge energy at the transmitter. the equalized signal is dc restored, thereby restoring its logic threshold to its corrective level regardless of shifts due to ac coupling. gennum corporation 521 - 63 - 05 8 gs9025 2. signal strength indication/carrier detect the gs9025 incorporates an analog signal strength indicator/carrier detect (ssi/cd) output indicating both the presence of a carrier and the amount of equalization applied to the signal. the voltage output of this pin versus cable length (signal strength) is shown in figures 2 and 12. with 0m of cable (800mv input signal levels), the ssi/cd output voltage is approximately 4.5v. as the cable length increases, the ssi/cd voltage decreases linearly providing accurate correlation between the ssi/cd voltage and cable length. fig. 12 when the signal strength decreases to the level set at the "carrier detect threshold adjust" pin, the ssi/cd voltage goes to a logic "0" state (0.8 v) and can be used to drive other ttl/cmos compatible logic inputs. in addition, when loss of carrier is detected the sdo /sdo outputs are muted (set to a known static state). 3. carrier detect threshold adjust this feature has been designed for use in applications such as routers where signal crosstalk and circuit noise cause the equalizer to output erroneous data when no input signal is present. the use of a carrier detect function with a fixed internal reference does not solve this problem since the signal to noise ratio on the circuit board could be significantly less than the default signal detection level set by the on chip reference. to alleviate this problem, the gs9025 provides a user adjustable threshold to meet the unique conditions that exist in each user's application. override and internal default settings have also been provided to give the user total flexibility. the threshold level at which loss of carrier is detected is adjustable via external resistors at the cd_adj pin. the control voltage at the cd_adj pin is set by a simple resistor divider circuit ( see typical application circuit ). the threshold level is adjustable from 200m to 350m. by default (no external resistors), the threshold is typically 320m. in noisy environments, it is not recommended to leave this pin floating. connecting this pin to v ee disables the sdo /sdo muting function and allows for maximum possible cable length equalization. 4. output eye monitor the gs9025 also provides an 'output eye monitor' (oem) which allows the verification of signal integrity after equalization, prior to reslicing. the oem pin is an open collector current output that requires an external 50 ? pullup resistor. when the pullup resistor is not used, the oem block is disabled and the internal oem circuit is powered down. the oem provides a 100mvp-p signal when driving a 50 ? oscilloscope input. 5. reclocker the reclocker receives a differential serial data stream from the internal multiplexer. it locks an internal clock to the incoming data and outputs the differential pecl retimed data signal and recovered clock on outputs sdo /sdo and sco /sco, respectively. the timing between the output and clock signals is shown below. fig. 13 the reclocker contains four main functional blocks: the phase locked loop, frequency acquisition, logic circuit, and auto/manual data rate select. 5.1. phase locked loop (pll) the phase locked loop locks the internal pll clock to the incoming data rate. a simplified block diagram of the pll is shown below. the main components are the vco, the phase detector, the charge pump, and the loop filter. 0 1 2 3 4 5 50 100 150 200 250 300 350 400 450 500 ssi/cd output voltage (v) cable length (m) 0 cd_adj control range sdo sco 50% gennum corporation 521 - 63 - 05 9 gs9025 fig. 14 5.1.1. vco the vco is a differential low phase noise, factory trimmed design that provides increased immunity to pcb noise and precise control of the vco center frequency. the vco operates between 30 and 540mb/s and has a pull range of 15% about the center frequency. a single low impedance external resistor, r vco , sets the vco center frequency ( see figure 15 ). the low impedance r vco minimizes thermal noise and reduces the pll's sensitivity to pcb noise. for a given r vco value, the vco can oscillate at one of two frequencies. when smpte = ss0 = logic 1, the vco center frequency corresponds to the ? l curve. for all other smpte/ ss0 combinations, the vco center frequency corresponds to the ? h curve ( ? h is approximately 1.5 x ? l ). fig. 15 the recommended r vco value for auto rate smpte 259m applications is 365 ? . the vco and an internal divider generate the pll clock. divider moduli of 1, 2, and 4 allow the pll to lock to data rates from 143mb/s to 540mb/s. the divider modulus is set by the auto/man , smpte, and ss[2:0] pins (see auto/manual data rate select section for further details) . in addition, a manually selectable modulus 8 divider allows operation at data rates as low as 30mb/s. 5.1.2. phase detector the phase detector compares the phase of the pll clock with the phase of the incoming data signal and generates error correcting timing pulses. the phase detector design provides a linear transfer function between the input phase and output timing pulses maximizing the input jitter tolerance of the pll. 5.1.3. charge pump the charge pump takes the phase detector output timing pulses and creates a charge packet that is proportional to the system phase error. a unique differential charge pump design insures that the output phase does not drift when data transitions are sparse. this makes the gs9025 ideal for smpte 259m applications where pathological signals have data transition densities of 0.05. 5.1.4. loop filter the loop filter integrates the charge pump packets and produces a vco control voltage. the loop filter is comprised of three external components which are connected to pins lf+, lfs, and lf-. the loop filter design is fully differential giving the gs9025 increased immunity to pcb board noise. the loop filter components are critical in determining the loop bandwidth and damping of the pll. choosing these component values is discussed in detail in the pll design guidelines section. recommended values for smpte259m applications are shown in the typical application circuit. 5.2. frequency acquisition the core pll is able to lock if the incoming data rate and the pll clock frequency are within the pll capture range (which is slightly larger than the loop bandwidth). to assist the pll to lock to data rates outside of the capture range, the gs9025 uses a frequency acquisition circuit. the frequency acquisition circuit sweeps the vco control voltage such that the vco frequency changes from -10% to +10% of the center frequency. figure 16 shows a typical sweep waveform. ddi/ddi lf+ lfs lf- r vco vco division r lf c lf1 c lf2 2 phase detector internal pll clock charge pump loop filter 0 100 200 300 400 500 600 700 800 0 200 400 600 800 1000 1200 1400 1600 1800 vco requency (mhz) r vco ( ? ) ? h ? l smpte=1 sso=1 gennum corporation 521 - 63 - 05 10 gs9025 fig. 16 the vco frequency starts at point a and sweeps up attempting to lock. if lock is not established during the up sweep, the vco is then swept down. the system is designed such that the probability of locking within one cycle period is greater than 0.999. if the system does not lock within one cycle period, it will attempt to lock in the subsequent cycle. in manual mode, the divider modulus is fixed for all cycles. in auto mode, each subsequent cycle is based on a different divider moduli as determined by the internal 3-bit counter. the average sweep time, t swp , is determined by the loop filter component, c lf1 , and the charge pump current, cp : the nominal sweep time is approximately 121 s when c lf1 = 15nf and cp = 165? (r vco = 365 ? ). an internal system clock determines t sys (see the logic circuit section) . 5.3. logic circuit the gs9025 is controlled by a finite state logic circuit which is clocked by an asynchronous system clock. that is, the system clock is completely independent of the incoming data rate. the system clock runs at low frequencies, relative to the incoming data rate, and thus reduces interference to the pll.the period of the system clock is set by the cosc capacitor and is: the recommended value for t sys is 450? (cosc = 4.7nf) 5.4. auto/manual data rate select the gs9025 can operate in either auto or manual data rate select mode. the mode of operation is selected by a single input pin (auto/man ). 5.4.1. auto mode (auto/man = 1) in auto mode, the gs9025 uses a 3-bit counter to automatically cycle through five (smpte=1) or three (smpte=0) different divider moduli as it attempts to acquire lock. in this mode, the ss[2:0] pins are outputs and indicate the current value of the divider moduli according to the table below. note that for smpte = 0 and divider moduli of 2 and 4, the pll can correctly lock for two values of ss[2:0]. 5.4.2. manual mode (auto/man = 0) in manual mode, the gs9025 divider moduli is fixed. in this mode, the ss[2:0] pins are inputs and set the divider moduli according to table 2. 6. locking the gs9025 indicates lock when three conditions are satisfied: 1. input data is detected 2. the incoming data signal and the pll clock are phase locked 3. the system is not locked to a harmonic v lf t swp t cycle t cycle = t swp + t sys t sys a t swp 4 c lf1 3i cp ----------------- = t sys 9.6 10 4 cosc [seconds] = table 1 auto/man = 1 (auto mode) ? h , ? l = vco center frequency as per figure 15. smpte ss[2:0] divider moduli pll clock 1 000 4 ? h /4 1 001 2 ? l /2 1 010 2 ? h /2 1 011 1 ? l 1 100 1 ? h 1 101 - - 1 110 - - 1 111 - - 0 000 4 ? h /4 0 001 4 ? h /4 0 010 2 ? h /2 0 011 2 ? h /2 0 100 1 ? h 0 101 - - 0 110 - - 0 111 - - gennum corporation 521 - 63 - 05 11 gs9025 the gs9025 defines the presence of input data when at least one data transition occurs every 1?. the gs9025 assumes that it is not locked to a harmonic if the pattern ? 101 ? or ? 010 ? (in the reclocked data stream) occurs at least once every t sys /3 seconds. using the recommended component values, this corresponds to approximately 150?. (in an harmonically locked system, all bit cells are double clocked and the above patterns become ? 110011 ? and ? 001100 ? , respectively.) 7. lock time the lock time of the gs9025 depends on whether the input data is switching synchronously or asynchronously. synchronous switching refers to the case where the input data is changed from one source to another source which is at the same data rate (but different phase). asynchronous switching refers to the case where the input data to the gs9025 is changed from one source to another source which is at a different data rate. when input data to the gs9025 is removed, the gs9025 latches the current state of the counter (divider modulus). therefore, when data is reapplied, the gs9025 begins the lock procedure at the previous locked data rate. as a result, in synchronous switching applications, the gs9025 locks very quickly. the nominal lock time depends on the switching time and is summarized in the table below: in asynchronous switching applications (including power up) the lock time is determined by the frequency acquisition circuit as described above. in manual mode, the frequency acquisition circuit may have to sweep over an entire cycle (depending on initial conditions) to acquire lock resulting in a maximum lock time of 2t cycle + 2t sys . in auto tune mode, the maximum lock time is 6t cycle + 2t sys since the frequency acquisition circuit may have to cycle through 5 possible counter states (depending on initial conditions) to acquire lock. the nominal value of t cycle for the gs9025 operating in a typical smpte 259m application is approximately 1.3ms. the gs9025 has a dedicated lock output (pin 39) indicating when the device is locked. it should be noted that in synchronous switching applications where the switching time is less than 0.5 s, the lock output will not be de-asserted and the data outputs will not be muted. 8. output data muting the gs9025 internally mutes the sdo and sdo outputs when the device is not locked. when muted, sdo /sdo are latched providing a logic state to the subsequent circuit and avoiding a condition where noise could be amplified and appear as data. the output data muting timing is shown in figure 17. fig. 17 ta b l e 2 auto/man = 1 (manual mode) ? h , ? l = vco center frequency as per figure 15. smpte ss[2:0] divider moduli pll clock 1 000 4 ? h /4 1 001 2 ? l /2 1 010 2 ? h /2 1 011 1 ? l 1 100 1 ? h 1 101 8 ? l /8 1 110 8 ? h /8 1 111 - - 0 000 4 ? h /4 0 001 4 ? h /4 0 010 2 ? h /2 0 011 2 ? h /2 0 100 1 ? h 0 101 1 ? h 0 110 8 ? h /8 0 111 - - table 3 switching time lock time < 0.5? 10? 0.5? - 10ms 2t sys > 10ms 2t cycle + 2t sys lock ddi sdo valid data no data transitions valid data outputs muted gennum corporation 521 - 63 - 05 12 gs9025 9. clock enable when clk_en is high, the gs9025 sco /sco outputs are enabled. when clk_en is low, the sco /sco outputs are tri-stated and float to v cc . disabling the clock outputs results in a power savings of 10%. it is recommended that the clk_en input be hard wired to the desired state. for applications which do not require the clock output, clk_en should be connected to ground and the sco /sco outputs should be connected to v cc . 10. stressfull data patterns all pll's are susceptible to stressful data patterns which can introduce bit errors in the data stream. pll's are most sensitive to patterns which have long run lengths of 0's or 1's (low data transition densities for a long period of time). the gs9025 has been designed to operate with low data transition densities such as the smpte 259m pathological signal (data transition density = 0.05). 11. pll design guidelines the reclocking performance of the gs9025 is primarily determined by the pll. thus, it is important that the system designer is familiar with the basic pll design equations. a model of the gs9025 pll is shown below. the main components are the phase detector, the vco, and the external loop filter components. fig. 18 11.1. transfer function the transfer function of the pll is defined as ? o / ? i and can be approximated as: equation 1 where and n is the divider modulus d is the data density (=0.5 for nrz data) i cp is the charge pump current in amps k ? is the vco gain in hz/v this response has 1 zero (w z ) and three poles (w p1 ,w bw ,w p2 ) where: the bode plot for this transfer function is plotted in figure 19. fig. 19 the 3db bandwidth of the transfer function is approximately: 11.2. transfer function peaking there are two causes of peaking in the pll transfer function given by equation 1. the first is quadratic: which has: and this response is critically damped for q = 0.5. loop filter ? i ? o vco cp r lf k pd c lf1 c lf2 phase detector 2 k ? + - ns ? o ? i ------ - sc lf1 r lf 1 + sc lf1 r lf l r lf --------- ? ?? ?? 1 + ---------------------------------------------------------------- 1 s 2 c lf2 ls l r lf --------- 1 ++ --------------------------------------------------------- = l n di cp k ? ------------------- - = w z 1 c lf1 r lf ---------------------- - = w p1 1 c lf1 r lf l r lf --------- ? -------------------------------------- - = w bw r lf l --------- = w p2 1 c lf2 r lf ---------------------- - = w z w p1 w bw w p2 frequency amplitude w 3db w bw 12 w bw w p2 ----------- - ? w bw w p2 ? () 2 12 w bw w p2 ----------- - ? --------------------------------- - + ---------------------------------------------------------------------- w bw 0.78 ----------- - = s 2 c lf2 ls l r lf --------- 1 ++ w o 1 c lf2 l -------------------- = qr lf r lf2 l ------------ = gennum corporation 521 - 63 - 05 13 gs9025 thus, to avoid peaking: or therefore, w p2 > 4 w bw however, it is desirable to keep w p2 as low as possible to reduce the high frequency content on the loop filter. the second is the zero-pole combination: this causes lift in the transfer function given by: to keep peaking to less than 0.05db: w z < 0.0057w bw 11.3. selection of loop filter components based on the above analysis, the loop filter components should be selected for a given pll bandwidth, ? 3db , as follows: 1. calculate where: i cp is the charge pump current and is a function of the r vco resistor and is obtained from figure 21. k ? = 90mhz/v for vco frequencies corresponding to the ? l curve. k ? = 140mhz/v for vco frequencies corresponding to the ? h curve. n is the divider modulus ( ? l , ? h and n can be obtained from table 1 or table 2) 2. choose r lf = 2(3.14) ? 3db (0.78)l 3. choose c lf1 = 174l/(r lf ) 2 4. choose c lf2 = l/4(r lf ) 2 fig. 20 11.4. spice simulations more detailed analysis of the gs9025 pll can be done using spice. a spice model of the pll is shown below: fig. 21 the model consists of a voltage controlled current source (g1), the loop filter components (r lf , c lf1 , and c lf2 ) a voltage controlled voltage source (e1), and a voltage source (v1). r2 is necessary to create a dc path to ground for node 1. v1 is used to generate the input phase waveform. g1 compares the input and output phase waveforms and generates the charge pump current, cp . the loop filter components integrate the charge pump current to establish the loop filter voltage. e1 creates the output phase waveform (phio) by multiplying the loop filter voltage by the value of the laplace transform (2 k ? /ns). the net list for the model is given below. the .param statements are used to set values for cp , k ? , n, and d. cp is determined by the r vco resistor and is obtained from figure 20. r lf c lf2 l ------------ - 1 2 -- - < 1 r lf2 c lf2 ------------------------- - l r lf --------- 4 > sc lf1 r lf 1 + sc lf1 r lf 1 r lf --------- ? ?? ?? 1 + ---------------------------------------------------------- s w z ------ - 1 + s w p1 --------- - 1 + ------------------- - = 20 log w p1 w z --------- - 20 log 1 1 w z w bw ----------- - ? --------------------- = l 2n i cp k ? --------------- = 0 50 100 150 200 250 300 350 400 0 200 400 600 800 1000 1200 1400 1600 1800 change pump current (?) r vco ( ? ) phii phio r2 e1 r lf c lf1 c lf2 g1 v1 2 k ? in+ in- ns 1 lf note: phii, phio, lf, and 1 are node names in the spice netlist. gennum corporation 521 - 63 - 05 14 gs9025 spice netlist * gs9025 pll model .param icp = 165e-6 kf= 90e+6 .param n = 1 d = 0.5 .param pi = 3.14 .ic v(phio) = 0 .ac dec 30 1k 10meg rlf 1 lf 1000 clf1 1 0 15n clf2 0 lf 15p e_laplace1 phio 0 laplace {v(lf)} {(2*pi*kf)/(n*s)} g1 0 lf value{d * icp/(2*pi)*v(phii, phio)} v1 2 0 dc 0v ac 1v r2 0 1 1g .end 12. i/o description 12.1. high speed analog inputs (sdi/sdi ) sdi/sdi are high impedance inputs which accept differential or single-ended input drive. figure 22 shows the recommended interface when a single- ended serial digital signal is used. fig. 22 12.2. high speed digital inputs (ddi/ddi ) ddi/ddi are high impedance inputs which accept differential or single-ended input drive. two conditions must be observed when interfacing to these inputs: 1. input signal amplitudes are between 200 and 2000 mv 2. the common mode input voltage range is as specified in the dc characteristics table. commonly used interface examples are shown in figures 23 through 25. figure 23 illustrates the simplest interface to the gs9025 digital inputs. in this example, the driving device generates the pecl level signals (800mv amplitudes) having a common mode input range between 0.4 and 4.6v. this scheme is recommended when the trace lengths are less than 1in. the value of the resistors depends on the output driver circuitry. fig. 23 when trace lengths become greater than 1in, controlled impedance traces should be used. the recommended interface is shown in figure 25. in this case, a parallel resistor (r load ) is placed near the gs9025 inputs to terminate the controlled impedance trace. the value of r load should be 2 times the value of the characteristic impedance of the trace. in addition, series resistors, r source , can be placed near the driving chip to serve as source terminations. they should be equal to the value of the trace impedance. assuming 800mv output swings at the driver, r load = 100 ? , r source = 50 ? and z o = 50 ? . fig. 24 figure 25 shows the recommended interface when the gs9025 digital inputs are driven single-endedly. in this case, the input must be ac-coupled and a matching resistor (z o ) must be used. fig. 25 when the ddi and the ddi inputs are not used, either pins 44 and 1 or pins 2 and 3 should be connected to v cc in order to saturate one input of the differential amplifier. 12.3. high speed outputs (sdo /sdo and sco /sco) sdo /sdo and sco /sco are current mode outputs that require external pullups ( see figure 26 ). the output signal swings are 800mv when 75 ? resistors are used. a diode can be placed between v cc and the pullups to shift the signal levels down by approximately 0.7 volts. when the output traces are longer than 1in, controlled impedance traces should be used. the pullup resistors should be placed at the end of the output traces as they terminate the trace in its characteristic impedance (75 ? ). fig. 26 sdi gs9025 sdi 75 10nf 10nf 75 113 ddi ddi gs9025 ddi ddi r source r load r source z o z o gs9025 ddi ddi z o gs9025 v cc sdo sdo sco sco 75 75 v cc 75 75 gs9025 gennum corporation 521 - 63 - 05 15 gs9025 typical application circuit ta b l e 4 : r vco = 365, ? h = 540mhz, ? l = 360mhz smpte ss[2:0] data rate (mb/s) loop bandwidth 1 000 143 850khz 1 001 177 1.40mhz 1 010 270 1.70mhz 1 011 360 3.0mhz 1 100 540 4.0mhz sdo sdo v ee sco sco v ee ss0 ss1 ss2 gs9025 top view agc+ v cc v ee lf+ lfs lf- v ee r vco _rtn r vco cbg v cc ddi ddi v cc_75 v cc v ee sdi sdi v cc v ee cd_adj agc- v cc_75 oem smpte a/d ssi/cd lock cosc v ee clk_en v cc v ee v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc 4 x 75 see note 2 from gs9024 see note 1 to gs9020 to led driver (optional) 1k 15n 0.1 0.1 5.6p 365 (1%) 1n 4.7n } v cc 10k 50 75 37.5 75 10n 10n 75 100k pot (optional) 100p power supply decoupling capacitors are not shown. auto/man v ee 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 all resistors in ohms, all capacitors in microfarads, unless otherwise stated. notes 1. it is recommended that the ddi/ddi inputs are not driven when the sdi/sdi inputs are being used. this minimizes crosstalk between the ddi/ddi and sdi/sdi inputs and maximizes performance. 2. these resistors are not needed if the internal pull-up resistors on the gs9020 are used. 521 - 63 - 05 16 gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 gennum japan corporation c-101, miyamae village, 2-10-42 miyamae, suginami-ku tokyo 168-0081, japan tel. +81 (03) 3334-7700 fax. +81 (03) 3247-8839 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no responsibility for the use of any circuits described herein and makes no representations that th ey are free from patent infringement. ?copyright august 1997 gennum corporation. all rights reserved. printed in canada. gs9025 package dimensions 10.00 ?.10 13.20 ?.25 pin 1 10.00 ?.10 0.80 bsc 0.45 max 0.30 min 13.20 ?.25 2.20 max 1.85 min 0.35 max 0.15 min 2.55 max 0.23 max. 1.60 ref 0.3 max. radius 0.13 min. radius 0.88 nom. 0.20 min 5? to 16? 5? to 16? 7? max 0? min 0? min 44 pin mqfp all dimensions in millimetres revision notes: clarified symbols for pin numbers 28, 29, 31, and 32; changed ssi/cd to ssi/cd. for latest product information, visit www.gennum.com document identification preliminary data sheet the product is in a preproduction phase and specifications are subject to change. caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation |
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